VLSI Implementation of Delayed LMS Adaptive Filter with Efficient Area-Power-Delay
1Muthulakshmi.G, M.E-Applied Electronics,, Dhanalakshmi Srinivasan College Of Engineering,Coimbatore, Tamilnadu, India.
2Revathi.S, Assistant Professor, Dhanalakshmi Srinivasan College Of Engineering, Coimbatore, Tamilnadu, India.
Manuscript received on January 05, 2014. | Revised Manuscript received on January 11, 2014. | Manuscript published on January 15, 2014. | PP: 10-13 | Volume-2 Issue-2, January 2014. | Retrieval Number: B0567012214/2014©BEIESP
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© The Authors. Published By: Blue Eyes Intelligence Engineering and Sciences Publication (BEIESP). This is an open access article under the CC BY-NC-ND license (http://creativecommons.org/licenses/by-nc-nd/4.0/)
Abstract: In this paper, we present an efficient architecture for the implementation of a delayed least mean square Adaptive filter. For achieving lower adaptation-delay and area-delay-power, we use a novel partial product generator and propose an optimized balanced pipelining across the time-consuming combinational blocks of the structure. From synthesis results, we find that the proposed design with less area-delay product (ADP) and less energy-delay product (EDP) than the best of the existing systolic structures, for various filter lengths. We propose an efficient fixed-point implementation scheme in the proposed architecture. We present here the optimization of design to reduce the number of pipeline delays along with the area, sampling period, and energy consumption. The proposed design is found to be more efficient in terms of the power-delay product (PDP) and energy-delay product (EDP) compared to the existing structures.
Keywords: Adaptive filters, Adder tree optimization, fixed-point arithmetic, least mean square (LMS) algorithms.