Design of Conditional Data Mapping Flip-Flop for Low Power Applications
Kanika Jindal1, Renu2, V. K. Pandey3

1Kanika Jindal, PG Student, Noida Institute Of Engineering & Technology, Greater Noida, (U.P.), India.
2Renu, Assistant Professor, Krishna Engineering College, Ghaziabad, (U.P.), India.
3Dr. V. K. Pandey, Professor, Noida Institute Of Engineering & Technology, Greater Noida, (U.P.), India
Manuscript received on April 05, 2013. | Revised Manuscript received on April 11, 2013. | Manuscript published on April 15, 2013. | PP: 72-75 | Volume-1 Issue-5, April 2013. | Retrieval Number: E0241041513/2013©BEIESP
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Abstract: Power consumption is a major bottleneck of system performance and it is listed as one of the top three challenges in International Technology Roadmap for Semiconductor 2008. In practice, a large portion of the on chip power is consumed by the clock system which is made of the clock distribution network and flip-flops. In this paper, various design techniques for a low power clocking system are surveyed. Among them minimizing a number of clocked transistor is an effective way to reduce capacity of the clock load. To approach this, we propose a conditional data mapping technique which reduces the number of local clocked transistors. A 24% reduction of clock driving power is achieved.
Keywords: Flip Flop, Low Power, CMOS Circuit.