Design D Flip-Flop for Low Power Application
Kumar Vinayak1, Owais Ahmad2
1Kumar Vinayak, MTech Scholar, Department of VLSI, Noida International University, Noida (U.P.), India.
2Owais Ahmad, Assistant Professor, Department of VLSI, Noida International University, Noida (U.P.), India.
Manuscript received on June 02, 2016. | Revised Manuscript received on June 11, 2016. | Manuscript published on June 15, 2016. | PP: 11-15 | Volume-4 Issue-6, June 2016. | Retrieval Number: F0994064616/2016©BEIESP
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© The Authors. Published By: Blue Eyes Intelligence Engineering and Sciences Publication (BEIESP). This is an open access article under the CC BY-NC-ND license (http://creativecommons.org/licenses/by-nc-nd/4.0/)
Abstract: Power consumption is a major problem of system performance and it is listed as one of the top three challenges in International Technology for Semiconductor. In practice, a large portion of the on chip power is consumed by the clock system which is made of the clock distribution network and flip-flops. In this thesis, various design techniques for a low power clocking system are surveyed. Among them minimizing a number of clocked transistor is an effective way to reduce capacity of the clock load. To approach this, we propose a conditional data mapping technique which reduces the number of local clocked transistors
Keywords: Flip Flop, Low Power, CMOS Circuit.