An Innovative Optical Transreciever Architecture for High Speed Data Interconnectivity Using CMOS IC for Optical Interconnects
Ashish Dixit1, R. K. Singh2
1Ashish Dixit, Department of Electronics & Comm. Engineering, Kumaon Engineering College (KEC), Dawarahat (Almora), Uttarakhand, India.
2Prof. R K Singh, Department of Electronics & Comm. Engineering, Kumaon Engineering College (KEC), Dawarahat (Almora), Uttarakhand, India.

Manuscript received on July 05, 2013. | Revised Manuscript received on July 11, 2013. | Manuscript published on July 15, 2013. | PP: 1-6 | Volume-1 Issue-8, July 2013. | Retrieval Number: H0354071813/2013©BEIESP
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Abstract: The high cost of the opto-electronics components which are typically used for the long-haul communication is prohibitive in the Fiber to the Home and Passive Optical Networks. This cost prone limitation can be easily optimized to some extent by reducing the cost of the electronics components used in the design of the transceiver and thereby, reducing the packaging cost. The ICs are designed in house and fabricated on a standard CMOS wafer with 0.18µm technology. These devices can operate at 1.8V and are low power in nature, thus reducing the demand on power dissipation. The transceiver module consists of an un-cooled and direct modulated laser diode driven, a high speed PIN photo-diode with amplifier and CMOS ICs. The CMOS ICs are attached on a transceiver substrate that is compliant with the small form-factor pluggable package multisource agreement and coupled to a 1310nm FP laser TOSA and a PIN ROSA with LC connector. This integrated transceiver is characterized up to 2.5-Gbps and can be applied in the high speed data transfer rate. The interconnect architectures which leverage high-bandwidth optical channels offer a promising solution to address the increasing chip-to-chip I/O bandwidth demands from the end user. A low-voltage integrating and double-sampling optical transreceiver’s front-end provides an adequate sensitivity in terms of power efficient simply, by avoiding linear high-gain elements common in conventional transimpedance amplifier. The phenomenon of clock recovery is performed with a dual-loop architecture which employs the baud-rate phase detection and feedback interpolation so as to achieve the reduced power consumption, while high-precision phase spacing is ensured at both the transmitter and receiver end through adjustable delay clock buffers. The increase in computing power enabled by CMOS scaling has created an increased demand for chip-to-chip I/O bandwidth. Unfortunately, the inter-chip electrical channel bandwidth has not scaled similarly to on-chip performance, causing current high-speed I/O link design to be channel limited that require sophisticated equalization circuitry which in turn increases the power consumption.
Keywords: 2.5-Gbps SFP, optical transceiver, 0.18µm CMOS technology, FTTH, GPON, Clock and data recovery, equalization, laser driver, optical interconnects, optical receiver, serial transceiver, VCSEL, 1.25G 1310nm optic transceiver; SFP; Signal Integrity; Circuit design, SDH, SONET, FEC, OTN.