Reusable Test bench for Network on Chip Router using Advanced Verification Methodologies
T Lakshmi Priyanka1, G .Deepthi2, B. Sunil Kumar3
1T Lakshmi Priyanka, She is Studding M.Tech in Mannan Institute of Science & Technology, Chevella, Ranga Reddy Dist (A.P), India.
2VDeepthi G, Assistant Professor, Dept of ECE, Mannan Institute of Science & Technology, Chevella, Ranga Reddy Dist (A.P), India.
3B. Sunil Kumar :He is Working as Associate professor and Head of Department of ECE in, Mannan Institute of Science & Technology, Chevella, Ranga Reddy Dist (A.P), India.
Manuscript received on August 05, 2013. | Revised Manuscript received on August 11, 2013. | Manuscript published on August 15, 2013. | PP: 70-74 | Volume-1 Issue-9, August 2013. | Retrieval Number: I0423081913/2013©BEIESP
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© The Authors. Published By: Blue Eyes Intelligence Engineering and Sciences Publication (BEIESP). This is an open access article under the CC BY-NC-ND license (http://creativecommons.org/licenses/by-nc-nd/4.0/)
Abstract: The focus of this Paper is the actual implementation of Reusable Network On Chip Router IP(Intellectual Property) and verifies the functionality of the five port IP router for System on chip applications using the latest verification methodologies(OVM,UVM,VMM) Hardware Verification Languages (Verilog, System Verilog),EDA tools. The Design of Network on Chip Router Implementing by using Verilog LRM as for Synthesis Environment. This Router design contains Four output ports and one input port, it is packet based Protocol. This Design consists of Registers, FSM and FIFO’s. The Verification goes on it finds functional coverage of the Network on Chip Router by using Verilog ,System Verilog using Questa-Sim 6.5e ,Synthesis is Xilinx ISE 9.2i EDA Tools.
Keywords: System Verilog, Fictional Coverage, assertions, Randomization, FIFO, FSM, Network-On-Chip, Verification Methodologies, Register blocks