Review on Designing of Multi Bit Flip-Flop to Achieve Reduced Area in VLSI Design
Yogita D. Bhole1, N. N. Thune2
1Yogita Bhole, Department of E&TC, Padmabhooshan Vasantdada Patil Institute of Technology, Pune, (Maharashtra), India.
2Prof. N. N. Thune, Department of E&TC, Padmabhooshan Vasantdada Patil Institute of Technology, Pune, (Maharashtra), India.
Manuscript received on July 10, 2015. | Revised Manuscript received on July 17, 2015. | Manuscript published on August 15, 2015. | PP: 1-2 | Volume-3 Issue-9, August 2015. | Retrieval Number: I0920083915/2015©BEIESP
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© The Authors. Published By: Blue Eyes Intelligence Engineering and Sciences Publication (BEIESP). This is an open access article under the CC BY-NC-ND license (http://creativecommons.org/licenses/by-nc-nd/4.0/)
Abstract: In this paper, we have designed Multi-bit Flip-flop (MBFF) and made performance comparison over the Single-bit Flip-flop (SBFF) We can increase Flip flop performance by merging clock pulse. But increase in clock pulse means it will increases the area. So the Multi-bit Flip-flop is designed by single clock pulse and achieves same functionality like two single-bit Flip-flop so it will reduce the area. The basic memory elements of designer considerations are Latch and flip flop. Optimizations in VLSI have been done on three factors: Area, Power and Timing (Speed). Area optimization means reducing the space of logic which occupy on the die. Memory elements play a vital role on Digital World but these elements consumes more area. Thus these elements can be designed using Multi-bit flip flop to reduce area.
Keywords: Flip-flop, Latch, Clock buffer, Clock network, Gate delay, Single bit flip flop, Multi bit flip flop.