The Design and Implementation of a Programmable Cyclic Redundancy Check (CRC) Computation Circuit Architecture Using FPGA
Rameshwr T. Murade1, MD. Manan Mujahid2, M.A.M. Sabir3
1Mr. Rameshwar T. Murade . MTech (ECE), SCET, Hyderabad, India
2Prof. MD. Manan Mujahid, Asst. Prof. & H.O.D, Dept. of ECE, SCET Hyderabad, India .
3Prof. M.A.M. Sabir , Asst. Prof., Dept. of ECE, SCET, Hyderabad, India.

Manuscript received on November 05, 2013. | Revised Manuscript received on November 2013 11, 2013. | Manuscript published on November 15, 2013. | PP: 14-19 | Volume-1 Issue-12, November 2013. | Retrieval Number: L05171111213/2013©BEIESP

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Abstract: Many communication systems use the cyclic redundancy code (CRC) technique for protecting key data fields from transmission errors by enabling both single-bit error correction and multi-bit error detection.[6] Cyclic redundancy check (CRC) coding is an error-control coding technique for detecting errors that occur when a message is transmitted. Data integrity is imperative for many network protocols, especially data-link layer protocols.[4] Techniques using parity codes and Hamming codes can be used for data verification, but CRC is the preferred and most efficient method used for detecting bit errors produced from medium related noise. For example, Ethernet uses a 32-bit CRC polynomial for error detection. Data storage is another area where CRC error detection is becoming increasingly important. iSCSI implementations that utilize the TCP/IP protocol to implement Storage Area Networks (SANs) require error detection to be deployed. These operate using multi-gigabit connection speeds and thus require CRC checks to be executed at high speed as well. [9]
Keywords: CRC, Error Correction, implementation with CRC 32, FPGA CRC.